library IEEE;
use ieee.std_logic_1164.all;

package package_alu is
	component logic_unit is
	port(a, b: in	std_logic_vector (7 downto 0);
		 sel : in	std_logic_vector (2 downto 0);
		 y	 : out	std_logic_vector (7 downto 0)
		 );
	end component;
	
	component arit_unit is
	port(a, b: in	std_logic_vector (7 downto 0);
		 sel : in	std_logic_vector (2 downto 0);
		 cin : in    std_logic;
		 y	 : out	std_logic_vector (7 downto 0)
		 );
	end component;
	
	component mux is
	port(a,b		: IN	STD_LOGIC_VECTOR(7 downto 0);
		 sel		: IN 	STD_LOGIC;
		 z  		: OUT	STD_LOGIC_VECTOR(7 downto 0)
		 );
	end component;
end package_alu;
